Topic:Design for Testability for Integrated Circuits
Abstract:Moore’s Law is helping pack ever more functionality and circuitry onto a silicon wafer. This makes access and testing of the highly embedded devices more difficult. This presentation will cover what is design for testability as it applies to digital designs, some fundamental test theory, and common DFT methodologies as practiced today. Slides
Speaker:Luis Basto
Speaker’s Bio:Luis is a member of the Front-End Solutions team at Cadence Design Systems. The primary focus of his current job is to help customers resolve front-end design issues particularly in the area of DFT. Luis has over 23 years of design and DFT experience in the semiconductor industry working for Motorola, AMD, Analog Devices, Texas Instruments, and Cadence. He has worked as an individual contributor as well as managed design teams globally. He is a Senior Member of the IEEE and has been awarded 6 US patents in the area of design and DFT. He has a BSEE from the University of Houston and an MSEE from Southern Methodist University.
Date & Time:Wednesday, November 16, 2011 : networking at 6:00 p.m., business and program from 7:00 to 8:30 p.m.
Location:PoK-e-Jo’s, 2121 W. Parmer Lane at Lamplight Village, Austin, TX 78727
Map:map
Cost:$5.00 minimum charge for the restaurant. Supper is at optional extra cost.
Reservations:Not required. All interested parties are invited to attend.
RSVP and for more information:Please email to ctcnaustin at gmail dot com.