2-Hour Short Course: Reliability Physics and Failure Mechanisms in Electronics Packaging 🗓

2-Hour Short Course: Reliability Physics and Failure Mechanisms in Electronics Packaging

Speaker: Xuejun Fan, Regents’ Professor, Department of Mechanical Engineering, Lamar University Meeting Date: Wednesday, November 2, 2022

Time: Checkin via WebEx at 7:45 AM; Presentation 8:00 – 10:00 AM (PDT)

Cost: none

Reservations: eps2211a.eventbrite.com

Summary: This course presents an overview of the physics of failures in electronics packaging. The course discusses key fundamental concepts of reliability physics associated with various stress conditions, including thermal degradation, thermo-mechanical stress, dynamic and vibrational loading, moisture and humidity, as well as electrical current stress. Failure mechanisms studied include chip-package interactions, micro-bump reliability, electromigration performance, inter-layer dielectric (ILD) damage under bumps and Cu pillars, solder joint reliability, drop and vibrational damage, interfacial delamination, and the impact of moisture and environmental humidity. Acceleration factor models for different failure mechanisms are introduced. Stress analysis methods using finite element analysis (FEA) with specific applications to packaging are described.

Course Outline:

Introduction to advanced package reliability physics
Thermal and thermo-mechanical driven failure mechanisms
Dynamic and vibrational-driven damages
Moisture and humidity-induced failures
Electromigration
Summary

For further presentations on reliability for electronics and photonics packaging, please attend REPP, November 9-10, 2022.

Bio: Xuejun Fan is a Regents’ Professor of the Texas State University System, the Mary Ann and Lawrence E. Faust endowed chair professor in the Department of Mechanical Engineering at Lamar University, Beaumont, Texas. He received his Ph.D. degree in solid mechanics from Tsinghua University, Beijing, China in 1989. His interests and research lie in the area of modeling, characterization, and reliability in heterogeneous integration in microelectronics. Dr. Fan had extensive experience in the semiconductor packaging industry, such as with Intel Cooperation, Philips Research, and the Institute of Microelectronics (IME), Singapore. Dr. Fan received the Outstanding Sustained Technical Contribution Award in 2017, and the Exceptional Technical Achievement Award in 2011 from IEEE Electronics Packaging Society (EPS). He is an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology and Microelectronics Reliability. Dr. Fan is an IEEE Fellow and a Distinguished Lecturer. He serves as chair, co-chairs, and committee members of various conferences such as ECTC, EPTC, ESTC, EuroSimE, ICEPT, ESREF, and EMPT. He has published more than 300 papers, including 4 books, over 100 journal papers, many book chapters, and numerous conference papers. Dr. Fan currently serves as a member-at-large of the IEEE Electronic Packaging Society (EPS) Board of Governors, and a co-chair of Modeling and Simulation in Heterogeneous Integration Roadmap (HIR).

Title:

Reliability Physics and Failure Mechanisms in Electronics Packaging

Excerpt:

— stress conditions, thermo-mechanical, vibrational, moisture, humidity, electromigration, acceleration factors, applications …

Packaging of Bioelectronic Implants: Key Building Blocks and Recent Advances 🗓

Speaker: P M Raj, Florida International University, Miami
Meeting Date: Thursday, September 15, 2022
Location: On the Internet
Time: Checkin via WebEx at 1:50 PM; Presentation at 2:00 PM (CDT)
Cost: none
Reservations: eps2209.eventbrite.com
Summary: Bioelectronic implants rely on wireless power and data telemetry for detecting physiological signals and communicating them to an external reader or an implanted module for close-loop therapeutic solutions. Sensor fusion and wireless connectivity with external electronic readers through simplified circuit topologies, advanced telemetry components for better signal sensitivity at low power, and 3D package integration for miniaturization and reliability are the main barriers for wireless neural recording. On the other hand, power telemetry and capacitor integration, high-density electrode arrays with high charge-injection and low impedance are critical for neurostimulation. This talk will highlight advances in the component and embedding technologies to realize performance, long-term stability and reliability while meeting the critical system scaling trends in bioelectronic implants. The talk will specifically cover key building blocks: a)Telemetry components and their heterogeneous integration to meet the power density and data rate needs, b) Bioelectronic component embedding with flexible fan-out interconnections, c) Low-impedance electrodes or impedance-transforming signal interfaces for better signal sensitivity, d)hermetic feedthroughs and remateable connectors to achieve the performance and reliability targets with robustness. The impact of these building blocks in creating future neurotechnologies will be illustrated through specific examples.

Bio: P. M. Raj’s expertise is in packaging of electronic and bioelectronic systems, with emphasis on nanoscale RF, power and bioelectronic components, and active and passive integration in ultrathin embedded modules. He is an Associate Professor in Biomedical Engineering and Electrical and Computer Engineering at Florida International University. He demonstrated several electronic packaging technologies, working with the whole electronic ecosystem, which include several semiconductor, packaging and material, tool, and end-user companies. He is widely recognized for his contributions in integrated passive components and technology roadmapping, component integration for bioelectronic, power and RF modules, and also for promoting the role of nanomaterials and nanostructures for electronics packaging applications through IEEE NTC and EPS activities. His research led to more than 340 publications, which include 8 patents. He co-advised and mentored more than 30 MS and PhD students who are current leaders and technology pioneers in the electronic packaging industry. He received ~30 best-paper awards in IEEE packaging and nanotechnology conferences and workshops. He delivered several invited lectures and offered several industry short courses. He is the Chair of Nanopackaging Technical Committee, EPS Representative of IEEE Nanotechnology Council, IEEE Distinguished Lecturer in Nanotechnology for 2020-2021, Associate Editor for IEEE Nanotechnology Magazine and Transactions of Components, Packaging and Manufacturing Technologies (T-CPMT). He earned his PhD from Rutgers University in 1999 in Ceramic Engineering, ME from the Indian Institute of Science, Bangalore and BS from the Indian Institute of Technology, Kanpur (1993).

Semiconductor Packaging: The Future Is Now 🗓

Speaker: Prof. Madhavan Swaminathan, Director, 3D Systems Packaging Research Center (PRC), Georgia Tech
Meeting Date: Friday, June 24, 2022
On-demand video: (48:50 + Q&A)
Summary: The recent buzz in the semiconductor industry is all about advanced packaging, a heterogeneous platform that enables the integration and miniaturization of systems. With supply chain shortages and most of semiconductor manufacturing being done off-shore, there is a wake-up call by the US government to regain US leadership and competitiveness in this upcoming area. This is a prime opportunity for US universities to step-in and drive innovation, transition these innovations into manufacturing, while creating the next workforce. The fundamental challenge, however, is that few universities in the United States have research and educational programs in semiconductor packaging!
After providing a brief introduction into the reasons why heterogeneous integration using semiconductor packaging is a means to continue Moore’s law, I will present on some of our recent advances and contributions in System on Package (SoP) technologies, a concept that we have been pioneering for almost three decades, that has relevance to emerging applications in Artificial Intelligence, Wireless Communications, Automotive, and Harsh Environments. I will also summarize some of our activities in curriculum development along with a snapshot of the Packaging Research Center, a graduated NSF Engineering Research Center (ERC) currently in its 28th year.
Bio: Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT) (http://www.prc.gatech.edu). He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning (CAEML: https://publish.illinois.edu/advancedelectronics/) and Theme Leader for Heterogeneous Integration, at the SRC JUMP ASCENT Center (https://ascent.nd.edu/). Prior to joining GT, he was with IBM working on packaging for supercomputers.
He is the author of 550+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS) currently in its 20th year. He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He received his MS and PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.

Heterogeneous 3D Nanoscale Components and Integration for Power, RF and Bioelectronic Functions 🗓

The IEEE EPS (Electronics Packaging Society) Dallas Chapter is sponsoring a technical presentation on Heterogeneous 3D Nanoscale Components and Integration for Power, RF and Bioelectronic Functions. The presenter is Professor Markondeyaraj (Raj) Pulugurtha. Details on the presentation are below (abstract and bio). Webex details below as well.

Heterogeneous 3D Nanoscale Components and Integration for Power, RF and Bioelectronic Functions

Abstract: Heterogeneous component integration with seamless and 3D connectivity between digital, RF, analog and passive components in a single package with high bandwidth at lower power is the key to realize future electronic and bioelectronic systems. This talk describes the recent nanomaterial and nanoscale component integration breakthroughs that are making heterogeneous integration a reality. Nanomagnetic inductors, high surface area nanocapacitors and innovative 3D component designs will be described for integrated power delivery. The second part focuses on material and component integration technologies for high-bandwidth 5G communications. include high-gain antenna arrays in a package with integrated power dividers and combiners, integrated electromagnetic interference isolation structures between power amplifier (PA) and low-noise amplifier (LNA) interconnects and integrated nanomagnetic and nanodielectrics for nonreciprocal and tunable components. The last part of the presentation describes nanopackaging technologies to enable bioelectronic systems with seamless integration between neural recording arrays, active devices and wireless interfaces for ultra-miniaturized wearable and implantable bioelectronic systems. Specific advances in system-in-flex packages for wearable electronics, miniaturized power telemetry and low-impedance electrodes will be discussed.

Biography: Dr. P. M. Raj‘s expertise is in packaging of electronic and bioelectronic systems, with emphasis on nanoscale RF, power and bioelectronic components, and active and passive integration in ultrathin embedded modules. He is an Associate Professor in Biomedical Engineering and Electrical and Computer Engineering at Florida International University. He demonstrated several electronic packaging technologies, working with the whole electronic ecosystem, which include several semiconductor, packaging and material, tool, and end-user companies. He co-led the development of world’s first 3D glass LTE diversity module, and 3D glass antenna-integrated package module for 5G mm wave applications. He developed advanced substrate-integrated power inductors and power capacitors for integrated power modules and voltage regulators. He is widely recognized for his contributions in integrated passive components and technology roadmapping, component integration for bioelectronic, power and RF modules, and also for promoting the role of nanomaterials and nanostructures for electronics packaging applications through IEEE NTC and EPS. His research led to 340 publications, which include 8 patents. He received more than 30 best-paper awards. He is the Chair of Nanopackaging Technical Committee, EPS Representative of IEEE Nanotechnology Council, IEEE Distinguished Lecturer in Nanotechnology for 2020 and 2021, Associate Editor for IEEE Nanotechnology Magazine and Transactions of Components, Packaging and Manufacturing Technologies (TCPMT). He earned his BTech from IIT Kanpur (1993), ME from IISc, Bangalore (1995) and PhD from Rutgers University (1999).

Growth in Semiconductor Packaging and Assembly: Are We in Another “Roaring 20s”? 🗓

Co-sponsored with the Silicon Valley EPS Chapter
Speaker: E. Jan Vardaman. TechSearch International, Inc.

Meeting Date: Thursday, December 16, 2021
Location: On the Internet
Time: Checkin via WebEx at 1:50 PM; Presentation at 2:00 PM (CST)
Cost: none
Reservations: eps2112a.eventbrite.com
Summary: With strong growth in 2021 for the electronics industry will 2022 see continued expansion? What are the growth drivers and which packages will support this growth. Will 5G smartphones and infrastructure growth continue? Will growth in the server and PC market remain strong? How do the trend in the adoption of electric vehicles change the dynamics? The industry is currently experiences shortages of substrates and leadframes. Will these shortages continue or will they be resolved? This presentation discusses these trends and more.
Bio: E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow. She is a member of MEPTEC, SMTA, and SEMI. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

Chiplet-in-Wafer Technology for the Development of III-V RF ICs 🗓

Co-sponsored by the Silicon Valley and San Diego EPS chapters
Speaker: Florian Herrault, PhD, HRL Laboratories, LLC
Meeting Date: Thursday, December 9, 2021
Location: On the Internet
Time: Checkin via WebEx at 1:50 PM; Presentation at 2:00 PM (CST)
Cost: none
Reservations: eps2109b.eventbrite.com
Summary: New requirements for communication (e.g., 5G) and radar (e.g., automotive) applications at millimeter-wave frequencies have fostered the development of new packaging solutions for circuit and subsystem manufacturing. In the area of RF compound semiconductors, technologies for the co-integration of high-performance devices and silicon circuits have also emerged.
HRL is developing a technology called MECAMIC (Metal Embedded Chiplet Assembly for Microwave Integrated Circuits) that uses GaN transistor chiplets integrated in the volume of passive interposer wafers. Engineering advances in chiplet manufacturing and assembly will be presented, along with a Process Design Kit and circuit demonstrators up to W-band.
Bio: Florian Herrault received his B.S. and M.S. degrees in physics and materials science from the National Institute of Applied Sciences (INSA), Toulouse, France, in 2003 and 2005, respectively. He received his Ph.D. degree in electrical and electronics engineering from the University of Toulouse, Toulouse, in 2009 while doing his research at the Georgia Institute of Technology. From 2009 to 2013, he was a Research Engineer and the Deputy Director with the MicroSensors and MicroActuators Group, Georgia Tech. Since 2013, he has been with HRL Laboratories, LLC, Malibu, CA, where he is the leader of the Advanced Packaging Solutions Group in the RF, E/O, and IR subsystems Department. He also holds the position of strategy lead for RF GaN. He is an active IEEE member, currently serving on the Executive Committee of the IEEE ECTC conference, and as a committee member of the IEEE IMS conference.

Activities

The goal of the Region 5 Chapter will be to facilitate IEEE-EPS relevant activities locally. Our charter is to generate interest in benefiting the community through education, networking, and professional development. The activities we are planning in our first six months are:

Reaching out to local members in raising awareness of this new Chapter.
Conducting surveys and interviews to help us identify the technical and social needs and interests of Chapter members. The results of these surveys should help us plan activities accordingly while focusing on the locale’s profile.
Holding two meetings allowing members to meet each other and network.
Additionally, we plan to initiate and follow through with the following activities to keep the members and volunteers excited. These are:
Organize inter-chapter joint meetings, seminars, symposiums, and webinars.
Arrange for guest speakers, develop workshops, and plan for social functions.
Invite academia, industry, and IEEE distinguished lecturers.
Provide valuable opportunities for members to network at a local level, enabling personal and professional growth.
Facilitate academic/industry collaboration and soliciting local government/academic support of chapter activities.