CIS & CIR, EMC, and CU Boulder: Interconnection Scaling – Going Big and Going Small
Room: KOBL 352, Bldg: Rustandy Building, 1111 Engineering Dr, Boulder, Colorado, United States, 80309Title: Interconnection Scaling – Going Big and Going Small Abstract: This presentation will cover a high-level overview of interconnections between integrated circuits – trends over the past several decades and what technologies may support future trends, along with a discussion of basic signal integrity considerations for such interconnections. Over most of the past 50 years the scaling of silicon integration was the winning hand for increased performance with packaging and interconnections scaling at substantial lower rates. Fundamental challenges in nanometer process nodes have effectively ended the steadily increasing benefits of Moore’s Law so new paradigms for 2D, 2.5D, and 3D Heterogeneous Integration packaging technologies are being proposed and developed to keep system performance scaling moving forward. Rapidly moving a lot of data between chips is fundamental to all these approaches. One approach for dense, high bandwidth interconnections will be discussed in some detail to illustrate tradeoffs and discuss the limits of how interconnections between chips can reach the limits of interconnections within chips. Co-sponsored by: University of Colorado Boulder Agenda: 6:30PM - 7:00PM Social 7:00PM - 8:00PM Technical Talk Room: KOBL 352, Bldg: Rustandy Building, 1111 Engineering Dr, Boulder, Colorado, United States, 80309