Abstract: As semiconductor manufacturing pushes against the limits of traditional monolithic chip design, chiplet-based architectures have emerged as a transformative solution for the industry. By breaking complex processors into smaller, discrete dies, manufacturers can significantly improve yields, reduce waste, and circumvent the hard reticle-size limitations imposed by modern lithography machines. This approach also unlocks powerful cost and efficiency advantages, allowing engineers to optimize each functional block by selecting the most appropriate manufacturing node, for example, pairing cutting-edge processes for high-performance logic with more cost-effective nodes for memory and I/O components.
Chiplet architectures, however, have brought renewed focus to the packaging that sits between the silicon die and the system PCB. These packages have had to increase in complexity to support many more chiplet-to-chiplet connections. Today’s advanced packages make it possible to combine specialized CPU, AI, and graphics modules within a single package. The ability to reuse proven chiplet designs and selectively upgrade individual functional blocks without redesigning an entire system represents a shift in how the semiconductor industry approaches processor development.
This talk will explore how chiplet technology is overcoming the manufacturing, economic, and design challenges facing the industry and shaping the future of advanced semiconductor packaging.
Parking: Parking information at CU Boulder will be provided to event registrants closer to the event date.
** The Front Range Speaker Series brings together students, faculty, IEEE members, and engineering professionals for technical talks from experts across industry and academia. This event is part of the ongoing speaker series co-hosted by the IEEE University of Colorado Boulder Student Branch and the IEEE Denver Section. This series is open to all levels from technical beginners to experts.
Upcoming Talks:
– Thursday, November 5, 2026:"Package and PCB Materials" by Darren Hitchcock (Panasonic)
– Thursday, December 3, 2026: Student presentations showcasing research and industry topics
Agenda:
Example Agenda
– 6:45–7:00 PM — Arrival and attendee check-in
– 7:00–7:10 PM — Welcome and speaker introduction
– 7:10–8:10 PM — Speaker presentation
– 8:10–8:20 PM — Q&A and discussion
– 8:20–8:30 PM — Closing remarks and upcoming speaker-series announcements
Room: ECCR 200, Bldg: Engineering Center, 1111 Engineering Drive, Boulder, Colorado, United States, 80309