Md Hasnine, PhD (Chapter Chair)

Dr. Md Hasnine is a staff packaging engineer at Qorvo focusing on innovative and developing next-generation RF/Microwave packaging solutions incorporating GaN, GaAs, SiC, and Si semiconductor devices. His work and research activities are in the field of advanced packaging, thermal solution, and other packaging technologies such as SiP/MCM, Flip chip Cu pillar GaN, WLCSP, air cavity packages as well as laminate and PCB technologies. His other area of work includes Ag/Cu sintering materials for a high-power package, solder alloy development, physical and mechanical properties of alloy, thermo-mechanical reliability of electronics under harsh environment, and failure analysis of electronic packaging. Prior to joining Qorvo, he worked as a power electronics packaging engineer at Ford Motor company. Previously, Md Hasnine was an R&D material research scientist at Kester with a focus on developing new lead-free solder alloy for semiconductor assembly and next-generation high-performance electronics. Before joining Kester, he worked as a post-doctoral researcher at National Energy Technology Laboratory (NETL). Hasnine received his PhD in Mechanical and Materials Engineering from Auburn University. He has published several journal and conference papers in the field of lead-free solder materials and electronic packaging reliability. He is the recipient of the best paper award at the Electronic Components and Technology Conference (ECTC) of the year 2014.

Rajen Murugan, PhD (Vice Chair)

Dr. Rajen Murugan specializes in developing multiphysics simulation and modeling methodologies for advanced semiconductor IC packaging and systems. He is currently a Distinguished Member of the Technical Staff (DMTS) with Texas Instruments, Inc. He has 24 patents (62 pending) and has published over 75 papers in peer-reviewed IEEE journals and conferences. Dr. Murugan holds a Ph.D. in Applied Electromagnetics from the University of Manitoba, Canada. He is an Affiliate Assistant Professor with the University of Washington EE Department, a Distinguished Lecturer for the IEEE Electronics Packaging Society (EPS), an Associate Editor for the IEEE Transactions on CPMT journal, a Senior Member of IEEE, the Vice Chair of the IEEE EPS Dallas Chapter, and the Chair of the IEEE Dallas Section (Region 5).

Kashyap Mohan, PhD (Chapter Secretary)

Dr. Kashyap Mohan is currently employed with Semiconductor Packaging Group at Texas Instruments. He leads the Advanced Packaging Development Lab at TI focusing on advanced packaging process development and demonstration. He received his PhD from Packaging Research Center, Georgia Institute of Technology in 2020. His key research interests are wafer level precision and MEMS packaging, sintered nanometals fine pitch interconnections. He has published 8 papers in peer reviewed journals and conferences.

Patrick Thompson, PhD

Dr. Pat Thompson is a Distinguished Member of the Technical Staff at Texas Instruments, where he leads the Packaging R&D team within the Semiconductor Packaging organization. He leads complex package technology platform projects from concept to implementation, drawing on more than 35 years of broad experience in the Semiconductor industry. Prior to joining Texas Instruments in 2001, Pat held technologist and management positions at Bell Labs, AMI Semiconductors, and Motorola Semiconductor (now NXP). He led advanced packaging research, development and transfer to manufacturing efforts in technologies ranging from flip chip fabrication and packaging, flip chip on board and chip scale packages, to multi-chip packaging, MEMS, optoelectronic packaging, GaAs and high-performance portable packaging. Pat earned his BS, MS and PhD in Chemical Engineering from the University of MO-Rolla (now MO Univ of Science and Technology). He has 11 issued patents and more than 30 publications, and has provided professional development courses at international conferences for more than 25 years. Pat is active in the IEEE, with leadership roles in the EPS (Electronic Packaging Society) and ECTC (Electronic Components and Technology Conference).

Jie Chen

Ms. Jie Chen is a Senior Member of Technical Staff (SMTS) in the Semiconductor Packaging group at Texas Instruments (TI). She focuses on the development and deployment of system-level modeling methodologies for SI/PI/EMC. She has trained more than 340+ engineers across TI on SI/PI/EMC Co-Design since 2013. She is currently working on Predictive EMC Modeling Flow development including CISPR25, BCI, DPI, etc. Before joining TI in 2012, she worked at Intel as an SI/PI Engineer for 5 years.

Tony Tang

Mr. Tony Tang is a seasoned IC packaging technologist currently working in Dallas, TX for AsteraLabs on high-performance data connectivity packaging solutions. Before his current role, he worked in Texas Instruments for 10 years where he developed numerous packages across multiple applications such as RF, data connectivity, power, Antenna on Package, data converters, etc. He has a wealth of multi-disciplinary background in signal and power integrity, package manufacturing and technology with the focus on FCBGA, SiP, and RF / high-speed packages. He received his MSEE degree from University of Florida in 2012 and he holds 30+ patents and is the author of 7 technical papers.

Harshpreet Bakshi, PhD (email) (Chapter Webmaster)

Dr. Harshpreet Bakshi received the B.Tech. degree in electronics and telecommunication engineering from Bharati Vidyapeeth University, Pune, MH, India, and the M.S. and Ph.D. degrees in electrical engineering from The University of Texas at Dallas, Richardson, TX, USA, in 2015, 2018 and 2022, respectively.
Between 2015 and 2022, he worked at Idea Cellular Ltd., CommScope Inc., Apple Inc. and at the Texas Analog Center of Excellence. He is currently a Semiconductor Packaging and Electrical Modeling Engineer with Texas Instruments Inc., Dallas, TX, USA. His research interests include mmWave and THz antenna design, semiconductor packaging, and system design.
Harshpreet serves as a reviewer of several journals and conferences of the IEEE AP-S, MTT-S and EP-S, and has held leadership positions at the IEEE EP-S Dallas and SSC-S UTD chapters.