Data Center CPU, GPU and AI accelerators have evolved from monolithic System-on-Chip designs to heterogenous System-of-Chiplets to enable “More-than-Moore” scaling of system-level performance and energy efficiency at lower costs. This presentation highlights importance of interdisciplinary System-Technology Co-Optimizations (STCO) for architecting such heterogenous System-of-Chiplets. We will discuss architecture and design considerations for optimizing compute, memory and interconnect components, as well as trade-offs and co-optimization opportunities with process/packaging technologies, power delivery, thermals and system architectures. We will also highlight future trends and innovations required to drive continued performance and efficiency improvements for the AI era. Virtual: https://events.vtools.ieee.org/m/534322