IEEE Central Texas Section

Design of analog CMOS circuits requires, obviously, a proper understanding of how MOS transistors work. Almost all design textbooks present incorrect small-signal models for MOS transistors. They emphasize Cgd, which is (for the intrinsic transistor) negligible in saturation, and completely ignore Cdg, which is the 2nd largest capacitance in saturation (where most MOS transistors in analog circuits operate). What is the difference between Cgd and Cdg? Why is the most important of these in saturation not Miller multiplied? Why are the gm and VDsat values that SPICE tells you wrong? Find out in this talk! Speaker(s): Colin McAndrew, Virtual: https://events.vtools.ieee.org/m/356178

Most decisions have two requirements: They should be “good”, and secondly when others are involved, they should be agreed to. The normative decision model provides a decision tree with 8 critical factors that determine, not what a decision should be, but how the decision should be made. This talk use a common, relevant scenario – whether or not to require a team to terminate remote work and return to the office – to walk through the model. The talk will end with a discussion on how the model generalizes and provides alternatives for anyone faced with the challenge of making a good decision. Speaker(s): Karl Arunski, Agenda: 6:00 to 6:10 PM - Open for participants to enter and network. 6:10 to 6:15 PM - IEEE LM and CTCN Business meeting and to introduce speaker. 6:16 to 7:30 PM - Formal Program and Q&A. Virtual: https://events.vtools.ieee.org/m/353808

Most decisions have two requirements: They should be “good”, and secondly when others are involved, they should be agreed to. The normative decision model provides a decision tree with 8 critical factors that determine, not what a decision should be, but how the decision should be made. This talk use a common, relevant scenario – whether or not to require a team to terminate remote work and return to the office – to walk through the model. The talk will end with a discussion on how the model generalizes and provides alternatives for anyone faced with the challenge of making a good decision. Speaker(s): Karl Arunski, Agenda: 6:00 to 6:10 PM - Open for participants to enter and network. 6:10 to 6:15 PM - IEEE LM and CTCN Business meeting and to introduce speaker. 6:16 to 7:30 PM - Formal Program and Q&A. Virtual: https://events.vtools.ieee.org/m/353808

5G represent a major departure from previous cellular generations. It will not only focus on speed, lower latency and spectrum efficiency but will also empower several verticals including IoT, AI/ML collecting and aggregating data for edge computing and with 6G at edge intelligence - Edge AI performing analysis and generating insightful information for critical actions in real-time or non-real-time applications. Speaker(s): Fawzi Behmann, Agenda: Talk: 6:30 PM to 7:30 PM Follow up questions: 7:30 PM to 8:00 PM Virtual: https://events.vtools.ieee.org/m/352011

In-Person Location: Ingram School of Engineering, San Marcos University, Room IGRM 4104 Virtual: Zoom (https://txstate.zoom.us/j/91084259333) Date: April 21, 2023 Time: 11:00 am – 1:00 pm Talk Title: “Efficient and Scalable Deep Learning Based Object Recognition Methods” Speaker: Mr. Vittal Siddaiah, Senior Engineering Lead, Intel F&B is included for in-person format Cost: none Abstract: Artificial Intelligence (AI) is the panacea for prescriptive and predictive analytics through Machine Learning (ML) techniques, demands for computational performance, and snowballing over the decades. Pattern Recognition is increasingly demanding in AI applications that include neural networks-based machine learning. In this research, we are dealing face recognition domain of pattern recognition and person detection, popularly classified under computer vision. Training deep-learning models are compute-intensive, and there is an industry-wide trend toward hardware specialization to improve performance. This research uses a DNN-based generic, efficient, scalable, and platform-independent framework that can be extendable across platforms. The proposed framework involves computer vision techniques suitable for unsupervised learning with low latency and high performance. The proposed framework is validated across diverse datasets, compatible and scalable across platforms, has low latency, and has a small footprint. The framework would serve as a benchmark and publish the rating parameters of response times, latencies, and accuracy that grade and differentiates various platforms. Bio: Vittal is a senior engineering lead at Intel with 19 years of experience architecting several silicon validation tools. He has led several designs of a validation tool suite for pre- and post-silicon validation. He is distinguished for his contributions to the machine learning-based, high-performance design of tools. Some of his innovations include defining metrics and measurements of power and performance. He has earned several recognitions and awards, including “One Generation Ahead Award” and “Waste Elimination Award.” Vittal has developed multiple teams, mentored leaders, and is passionate about mentoring engineers and students. He has won the “Best Trainer Award” at Intel. Some domains include Hardware-software co-design, Operations Research, Image Processing, Operating systems, System Design and Optimization, and High-Performance Computing. Vittal is an avid learner with his Masters in Electrical Engineering, Masters in Management, M Phil in Management, and Masters in Mathematics. If help is needed, please connect with: Prof. Semih Aslan, [email protected] or Fawzi Behmann, [email protected] Agenda: Agenda 11:00 am 11:35 am Introduction & Opening Remarks 11:35 am - 12:35 pm Talk & Q& A 12:35 pm - 12:50 pm Membership 12:50 pm - 1:00 pm Recap & Networking Room: IGRM 4104, Bldg: Ingram School of Engineering, 601 University Dr., San Marcos, Texas, United States, 78666, Virtual: https://events.vtools.ieee.org/m/357504